Cookie
This website requires cookies to provide all of its features. For more information on what data is contained in the cookies, please see our Privacy Policy page. To accept cookies from this site, please click the Accept button below.
| 供应商 | CAST |
|---|---|
| 型号 | GUNZIP/ZLIB/Inflate Data Decompression Core |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Compression Standards ZLIB (RFC-1950) Inflate/Deflate (RFC-1951) GZIP/GUNZIP (RFC-1952) Inflate/Deflate Features Up to 32KB history window size All deflate block types Static and Dynamic Huffman-Coded blocks Stored Deflate Blocks High Performance & Low Latency Three bytes per clock average processing rate, for throughputs exceeding 20Gbps with a single core, and scalable to more than 100Gbps with multiple core instances Latency from 20 clock cycles for Static Huffman blocks, and typically less than 2000 cycles for Dynamic Huffman Blocks Easy to Use and Integrate Processor-free, standalone operation Extensive Error Catching & Reporting for Smooth Operation and Recovery in the presence of Errors Header Syntax Errors CRC/Adler 32 Errors File Size Errors Coding errors Huffman Tables Errors Non-correctable ECC memory errors Optional ECC memories, necessary for Enterprise-Class RASM Streaming-capable, optionally bridged to AMBA AXI4-Stream interfaces Microcode-free, scan-ready design Configuration Options Synthesis time configuration options allow fine tuning the core's size and performance: Input and output bus width FIFO sizes Maximum History Window Static-Only or Dynamic and Static Huffman Tables support Two or three decompressed bytes per cycle throughput |
| 详情页 | View more |
| 附件链接 | View more |
ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards.
The core features fast processing, with low latency and high throughput. On average the core outputs three bytes of decompressed data per clock cycle, providing over 15Gbps in a typical 40nm technology. Designers can scale the throughput further by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps.The latency is in the order of few tens of clock cycles for blocks coded with static Huffman tables, and typically less than 2,000 cycles for block encoded with dynamic Huffman tables.
The decompression core has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data decompression. The core receives compressed input files and outputs decompressed files. No preprocessing of the compressed files is required, as the core parses the file headers, checks the input files for errors, and outputs the decompressed data payload. Featuring extensive error tracking and reporting errors, the core enables smooth system operation and error recovery, even in the presence of errors in the compressed input files. Furthermore, internal memories can optionally support Error Correction Codes (ECC) to simplify achievement of Enterprise Class reliability requirements.
The ZipAccel-D core is a microcode-free design developed for reuse in ASIC and FPGA implementations. Streaming data, optionally bridged to AMBA AXI4-stream, interfaces ease SoC integration. Technology mapping is straightforward, as the design is scan-ready, microcode-free, and uses easily replaceable, generic memory models. The core has been rigorously verified and production proven in a number of commercially available products.
The core features fast processing, with low latency and high throughput. On average the core outputs three bytes of decompressed data per clock cycle, providing over 15Gbps in a typical 40nm technology. Designers can scale the throughput further by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps.The latency is in the order of few tens of clock cycles for blocks coded with static Huffman tables, and typically less than 2,000 cycles for block encoded with dynamic Huffman tables.
The decompression core has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data decompression. The core receives compressed input files and outputs decompressed files. No preprocessing of the compressed files is required, as the core parses the file headers, checks the input files for errors, and outputs the decompressed data payload. Featuring extensive error tracking and reporting errors, the core enables smooth system operation and error recovery, even in the presence of errors in the compressed input files. Furthermore, internal memories can optionally support Error Correction Codes (ECC) to simplify achievement of Enterprise Class reliability requirements.
The ZipAccel-D core is a microcode-free design developed for reuse in ASIC and FPGA implementations. Streaming data, optionally bridged to AMBA AXI4-stream, interfaces ease SoC integration. Technology mapping is straightforward, as the design is scan-ready, microcode-free, and uses easily replaceable, generic memory models. The core has been rigorously verified and production proven in a number of commercially available products.
FAQ - Frequently Asked Questions
Welcome to Sparsh\'s FAQ! Here you\'ll find answers to our most asked questions. Still have something we should know? Send us an email, we\'re happy to help!
Q1: How can I change my shipping address?
A1: Consectetur morbi, suscipit donec semper vitae sed a class vivamus. Sodales montes porttitor adipiscing nisl sit dui sem fringilla elit. Sagittis lacinia montes nisl mollis lobortis cras nisi. Conubia montes odio taciti magnis morbi mauris lorem pulvinar mollis aliquam. Faucibus facilisi tempus tincidunt eu laoreet. Porta donec vitae suscipit habitasse fermentum vivamus!
- Eget est ad potenti primis id rhoncus vestibulum vestibulum. Ante est vel mattis mattis. Vel eleifend auctor lorem, odio proin quisque potenti parturient euismod. Tristique massa quis morbi netus magna pretium laoreet. Inceptos eget massa ac lacinia vitae suspendisse orci nascetur vel torquent. Feugiat eleifend eget aenean facilisi sapien proin leo dictumst semper orci ipsum? Ultrices duis tellus consequat nostra.
Q2: How do I activate my account?
A2: The instructions to activate your account will be sent to your email once you have submitted the registration form. If you did not receive this email, your email service provider’s mailing software may be blocking it. You can try checking your junk / spam folder or contact us at magento@sparsh-technologies.com
Q3: How do I cancel my orders before I make a payment?
A3: After logging into your account, go to your Shopping Cart. Here, you will be able to make a payment or cancel your order. We will not give refunds if payment is verified.
Q4: How long will it take for my order to arrive after I make payment?
A4: Members who ship their orders within Inida should expect to receive their orders within 2 working days upon payment verification depending on the count of orders received.
If you experience delays in receiving your order, contact us immediately and we will help to confirm the status of your order.
Q5: What are the payment methods available?
A5: At the moment, we only accept Credit/Debit cards and Paypal payments.
Q6: How do I make payments using Paypal? How does it work?
A6: Paypal is the easiest way to make payments online. While checking out your order, you will be redirected to the Paypal website. Be sure to fill in correct details for fast & hassle-free payment processing. After a successful Paypal payment, a payment advice will be automatically generated to Samplestore.com system for your order.
It\'s fast, easy & secure.