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| 供应商 | T2M |
|---|---|
| 型号 | Wide-band Analog-to-Digital Converter |
| 类型 | Hard IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | 14-bit Time-Interleaved Pipeline ADC 4.32GSps Sampling Rate 60dBFS SNR (9.7 ENOB) with 54MHz External AC coupling for the input signal Two power supplies: 1.8V for analog and 1.0V for digital compensation 1.0Vpp differential full-scale input Buffered analog inputs Input signal bandwidth: 54MHz to 1794MHz Power down mode Data ready output at 270MHz |
| 详情页 | View more |
| 附件链接 | View more |
This is a wide-band Analog-to-Digital Converter based on 16 Time-Interleaved Pipeline sub-ADC followed by a digital correction algorithm for gain, offset and skew correction. The differential input is terminated by a 100 Ohms resistor (100 Ohms differential) and followed by an input buffer driving the sub-ADC. The signal amplitude is 1Vpp differential. The analog source driving the ADC shall be ac-coupled to the input pins with two external capacitors of 1nF minimum. The input common-mode is generated internally. The input clock is a differential signal with amplitude of 800mVpp differential. The ADC includes two internal power supply regulators (LDO) for the analog part: - A 1.1v LDO with external decoupling capacitor to reach a high power rejection ratio - A 1.5v LDO with internal capacitor for the input buffer and biasing. The digital part is supplied by the external 1.0V.The digital corrector receives the 16 sub-ADC 12b outputs and delivers 14b for each output. Hence, the output data are organized in 16x14b–buses clocked at 270MHz (Fs/16). Each bus gives the data coming from a specific sub-ADC in a 2's complemented format (range is [-2N-1; 2N-1-1]). A data ready clock is provided at 270MHz (Fs/16).
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