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| 供应商 | Cadence |
|---|---|
| 型号 | The Cadence USXGMII PCS (PCSR_X) IP provides the logic required to integrate a USXGMII, 5GBASE-R, or 10GBASE-R PCS into any syst |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Also configurable as a 5GBASE-R or 10GBASE-R PCS compliant with IEEE 802.3 Clauses 49 and 129 ISO 26262 ASIL-B ready with automotive safety features (ASF) Optional BASE-R FEC (Clause 74) Programmable PRBS31 and PRBS9 (Clause 68) test pattern generators and error checkers Scrambled idle test pattern generator and checker Square wave test pattern generator 64b/66b encoding/decoding Optional clock tolerance compensation on receive (RX) path Connection to a 10 Gigabit Ethernet MAC using a demultiplexed XGMII interface Data scrambling on transmit (TX) path and descrambling on RX path |
| 详情页 | View more |
| 附件链接 | View more |
The Cadence USXGMII PCS (PCSR_X) IP provides the logic required to integrate a USXGMII, 5GBASE-R, or 10GBASE-R PCS into any system on chip (SoC). Compliant with the Cisco Universal SXGMII Interface for a Single Multi-Gigabit Copper Network Port and IEEE 802.3 Clause 49 standards, the PCS IP has several optional features to customize the physical coding sublayer (PCS) for the specific needs of any application. There are options to include support for BASE-R forward error correction (FEC), as per IEEE 802.3 Clause 74, and access to control and status registers through an APB interface. The PCS IP is engineered to be quickly and easily integrated into any SoC, and to connect seamlessly to a Cadence or third-party MAC through a demultiplexed XGMII (64-bit data, 8-bit control, single clock-edge interface). Connection to the SerDes is through a configurable 16-, 20-, 32-, 40-, or 64-bit interface.
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