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| 供应商 | Cadence |
|---|---|
| 型号 | Mature controller solution for OTG and Device applications |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Supports High-Speed (480Mbps) and Full-Speed (12Mbps) data transfer rates Scatter-gather DMA with AMBA AXI interface Up to 8 IN and 8 OUT configurable endpoints Certified for compliance with USB 2.0 specification AXI configuration interface Supports Link Power Management (L0 through L3) Supports Attach Detection Protocol Support for Remote Wake-Up |
| 详情页 | View more |
| 附件链接 | View more |
Certified for compliance with Universal Serial Bus Specification, Revision 2.0, the Cadence? Design IP for USB 2.0 Controller operates in High-Speed (480Mbps) and Full-Speed (12Mbps) modes. The PHY interface complies with USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, version 1.05. The Controller IP is architected to quickly and easily integrate into any system on chip (SoC), and to connect seamlessly to a Cadence or third-party UTMI-compliant PHY. Both configuration and data interfaces of the controller are compatible with industry-standard Arm? AMBA? AXI specifications. The Controller IP is delivered with a low-level driver to ease integration into the target application. The Controller IP supports all available USB 2.0 classes. The Controller IP is silicon-proven, and has been extensively validated with multiple hardware platforms. The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and systems and peripherals IP.
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