Universal Chiplet Interconnect Express (UCIe 1.0) Controller-ip-19709

¥10,000.00
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SKU
ip-19709
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供应商 Cadence
型号 Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols
类型 Soft IP
到期日 Available on request
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特征 Ultra-low latency controller for data intensive die-to-die applications Supports single and multiple PHY modules streaming, PCIe, and CXL protocols Data reliability through parity, CRC, retry (when applicable) Sideband messaging for link training and parameter exchange Link State Management and Protocol/Parameter Negotiation between the links Superior power efficiency and performance 512bit datapath for connection to cache fabric Optimized for quick and easy integration with a UCIe PHY for industry standard interoperability on the RDI and FDI interfaces Arbitration mux can be used to support multiple protocols such as CXL.io and CXL.cachemem
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The Cadence UCIe? Controller is a high-bandwidth, low-power and low-latency die-to-die solution that enables multi-die system in package integration for high performance compute, AI/ML, 5G, automotive and networking applications. The UCIe? physical layer includes the link initialization, training, power management states, lane mapping, lane reversal, and scrambling. The UCIe? controller includes the die-to-die adapter layer and the protocol layer. The adapter layer ensures reliable transfer through link state management and parameter negotiation of the protocol and flit formats. The UCIe? architecture supports multiple standard protocols such as PCIe, CXL and streaming mode.

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