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UHT-H264E-IDR, Scalable UHD H.264 Encoder-ip-21845
￥10,000.00
| 供应商 | ALMA Technologies |
|---|---|
| 型号 | Ultra-High Throughput - Intra (IDR) frames encoding |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Intra frames (IDR) only encoder with full compliance to the ITU-T H.264 specification. Constrained Baseline, Main, High 10 intra, High 4:2:2 intra, and High 4:4:4 intra (12 bit 4:2:2 or 4:2:0) profiles encoding. 4:2:0 and 4:2:2 YCbCr digital video input. 8-, 10- and 12-bit per component color depth encoding. ITU-T H.264 Annex B compliant NAL byte-stream output. Perceptually optimized Image Quality. Ultra-High throughput using scalable and transparent parallel processing. Advanced Intra prediction (all 16x16, 4x4 and Chroma modes). CQP - VBR and CBR encoding. One frame algorithmic encoding latency with deep sub-frame bitrate regulation for zero additional latency contribution to the end-to-end system latency. |
| 详情页 | View more |
| 附件链接 | View more |
The UHT-H264E-IDR IP core from Alma Technologies is a scalable ultra-high throughput H.264 encoder. It is designed to enable 4K UHD resolutions in power- and cost-effective FPGA and ASIC implementations. The UHT-H264E-IDR is an Intra frames (IDR) only encoder and has the smallest silicon footprint of all our UHT H.264 cores. This encoder is most suitable for applications requiring high video quality in relatively low compression ratio working range. Encapsulating the longstanding Alma Technologies expertise with H.264, the encoder offers perceptually optimized image quality and includes valuable technology, such as its high-quality low-latency encoding, using deep sub-frame bitrate regulation.
The UHT-H264E-IDR can be configured to support Baseline, Main and High profiles, 4:2:0 and 4:2:2 chroma sampling, and up to 12-bit per component color depth. It can be also used for high frame rate SD to Full HD interlaced or progressive video encoding. The core is very easy-to-use and integrate in a system. It is an autonomous, CPU/GPU-less, complete H/W implementation, accepting video input in standard raster scanned interleaved order and producing ready-to-use H.264 NAL byte-stream output.
The UHT-H264E-IDR is based on a scalable architecture that uses a configurable number of internal, parallel processing, engines. This is done in a way which is totally transparent to the system utilizing the IP, abstracting all the parallelization complexity from the rest SoC design and operation. In addition to the configurable number of internal engines that matches the throughput requirements to the available silicon speed, the encoder can be further fine-tuned before synthesis to save silicon area by removing features that are not needed in a certain implementation.
The UHT-H264E-IDR core implements a simple and flexible, requests based, external memory interface with independent read and write data paths. The external memory I/F is also designed to be tolerant to memory delays and latencies, which may be present in a shared memory system architecture.
Being carefully designed and rigorously verified the UHT-H264E-IDR is a reliable and easy-to-use and integrate IP.
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