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| 供应商 | T2M |
|---|---|
| 型号 | Revolutionary Quad SPI |
| 类型 | Hard IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Operates with 8, 16 and 32 bit CPUs Full duplex synchronous serial data transfer DMA support Support for 32, 16 and 8 bit systems Support for various system Bus Standards Single, Dual and Quad SPI transfer Multimaster system supported System error detection Interrupt generation Four transfer formats |
| 详情页 | View more |
| 附件链接 | View more |
The DQSPI is a revolutionary quad SPI designed to offer the fastest available operations for any serial SPI memory. It is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Moreover, IP Core supports all 8, 16, 32 bit processors available on the market. The DQSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It lets the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it’s capable of interprocessor communications in a multi?master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the four serial data lines. In the Single SPI mode data is simultaneously transmitted and received, in DUAL and QUAD SPI modes – data is shifted in or out on respectively two or four data lines at once. DCD’s IP Core is a technology independent design that can be implemented in a variety of process technologies. The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. Clock control logic allows a selection of clock polarity, phase and a choice of four fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects bit rates for the serial clock. The DQSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. Error?detection logic is included to support interprocessor communications. A write collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode?fault detector automatically disables DQSPI output drivers, if more than one SPI device simultaneously attempts to become bus master. The DQSPI supports two DMA modes: single transfer and multi?transfer. These modes allow DQSPI to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multi-ple byte transfers. DQSPI is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements.
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