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供应商	VeriSilicon
型号	SMIC 0.18um 1.8V/3.3V SSTL2/SSTL18 Combo I/O Cell Library
类型	Hard IP
到期日	Silicon proven
源网址	View more
特征	SMIC 0.18um Logic 1P6M Salicide 1.8V/3.3V process 1.8V core and 1.8V/2.5V external interface Operates up to 400MHZ (DDR) and 533MHZ (DDR2) Power down mode in input buffer Input buffer with hysteresis to increase noise immunity and stability On Die Termination (ODT) Resistor 50/75/150Ohm for SSTL18 Off-Chip Driver (OCD) Calibration with programmable output impedance for SSTL18 Suitable for four, five, six metal layers?physical design HBM 2KV ESD
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VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL2/SSTL18 Combo I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salicide 1.8V/3.3V process. This library is fully compliant with JESD8-9B Stub Series Terminated Logic for 2.5V (SSTL2) and JESD79E (DDR SDRAM specification); JESD8-15a Stub Series Terminated Logic for 1.8 Volts (SSTL_18) and JESD79-2B (DDR2 SDRAM specification). The SSTL2/SSTL18 provides MOS push-pull interface designs and is especially optimized for main stream memory applications. It is intended to improve operation in situations where busses must be isolated from relatively large stubs. SSTL2/SSTL18 has the advantages of lower voltage swing, lower power dissipation and higher immunity to generated noise because of the differential receiver.

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