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| 供应商 | VeriSilicon |
|---|---|
| 型号 | SMIC 0.13um 1.2v/3.3v |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | View more |
| 详情页 | View more |
| 附件链接 | View more |
VeriSilicon SMIC 0.13um DDRPHY_02 developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8M Salicide 1.2V/3.3V process.
This PHY solution is comprised of two hard macros, one OCD, one master DLL module and SSTLCOMBO_02 library.
One of the two hard macros is an individual 8bit data slice, the other is a command and address block. Each DDR solution must contain a minimum of one 16bit data block and a command and address block. Designers can flexibly configure external data bus width in 16bit increments by adding additional data slice to create a PHY with an arbitrary aspect ratio.
The OCD module adjusts driver impedance to match external resistor, and compensates impedance change caused by PVT fluctuation.
The Master DLL module has fine delay step granularity versus large 90 degree phase shift.
The SSTLCOMBO_02 library provides interfaces to DDR2 and DDR SDRAMs and supports from 100MHz to 400MHz clock frequency and 200~800Mbps data rate respectively. The chip to chip interface is accomplished via SSTL_18/_2 I/Os featuring on-die termination (ODT).
This PHY solution is comprised of two hard macros, one OCD, one master DLL module and SSTLCOMBO_02 library.
One of the two hard macros is an individual 8bit data slice, the other is a command and address block. Each DDR solution must contain a minimum of one 16bit data block and a command and address block. Designers can flexibly configure external data bus width in 16bit increments by adding additional data slice to create a PHY with an arbitrary aspect ratio.
The OCD module adjusts driver impedance to match external resistor, and compensates impedance change caused by PVT fluctuation.
The Master DLL module has fine delay step granularity versus large 90 degree phase shift.
The SSTLCOMBO_02 library provides interfaces to DDR2 and DDR SDRAMs and supports from 100MHz to 400MHz clock frequency and 200~800Mbps data rate respectively. The chip to chip interface is accomplished via SSTL_18/_2 I/Os featuring on-die termination (ODT).
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