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| 供应商 | VeriSilicon |
|---|---|
| 型号 | 533M, 50ps jitter |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Process: SMIC 0.13um Generic 1P 6/7/8M Single power supply: 1.2V Reference frequency range: 200 MHz to 533.3 MHz Programmable delay tuning around DQS? 90 degree delay. Low jitter output (less than 100ps for DDR or 50ps for DDR2 cycle to cycle jitter) Matching rise and fall time on the output signals. |
| 详情页 | View more |
| 附件链接 | View more |
The S13_DLL_01 is developed as a macro cell to generate two independent channels?programmable delay. The master block is the core DLL, which takes reference clock as input, running at DDR or DDR2 speed. The slave block consists of two 90 degrees delay lines which are controlled by Master block and the adjust pin. The slave block provides 2 output signals, each one is of 90 degrees delay to its DQS input signal, and renders minor delay tuning.
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