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供应商	Arasan Chip Systems
型号	PSRAM Host Controller IP
类型	Soft IP
到期日	Silicon proven
源网址	View more
特征	No configuration start. The PSRAM IP defaults into SPI mode (1S-1S-1S) upon reset, with a command 8’h03 and access to the first 16MB of external address space. AXI3 or AXI4 support, with a parameterized bus width ranging anywhere from 16 bits to 1024 bits wide. EXecute-In-Place Support (XiP). Full write strobe support in both legacy protocols, and when enabled in xSPI (8D) mode. The AXI support within this design has been formally verified to be protocol compliant.
详情页	View more
附件链接	View more

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详情

Arasan Chip System’s PSRAM master controller is designed to be a simple and hands off, yet high speed PSRAM controller. It makes reading from an external flash device, using this controller, as simple as reading from, or writing to, the main AXI3 or AXI4 slave port. An AXI4-lite control port provides access to both the raw xSPI interface, but it also provides the ability to control the SPI sub-protocol used for all subsequent transactions with great flexibility. Using the AXI4-lite port, the controller may be configured to support most SFDP protocols. This includes the ability to write to write to devices that support it. High speed DMA operation is possible via a separate AXI master port designed for that purpose.

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