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PCIe Multifunction IP for XILINX 7 FPGAs-ip-22720
￥10,000.00
| 供应商 | Smartlogic GmbH |
|---|---|
| 型号 | The PCI Express Specification allows Endpoints that incorporate more than one physical PCIeFunction. |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Extends the Xilinx integrated PCI-Sig compliant PCIe hardblock by up to 6 true physical PCI Express Functions (not virtual functions requiring SRIOV capability) Designs provides up to 8 AXI Masters which can be freely mapped to the PCIe functions Optional DMA support (Flex or HCC IP core) The user defines, if all PCIe functions communicate with either the same or with a different device driver 32 and 64-Bit BAR support for all functions BARs can be defined independently at compile time. Each function can issue interrupts (MSI only) Detection of signal integrity problems on PCIe link (for productional testing) Link Speeds Gen 1 or 2, Link Width x1; Device driver package available as option Available for A7, K7 and Zynq-7000 (ask for the availability for other FPGA families) |
| 详情页 | View more |
| 附件链接 | View more |
The PCI Express specification allows endpoints
that incorporate more than one physical PCIe function. Such endpoints are called multi function devices. The big advantage of a multi function device is, that a separate device driver
can be associated to each physical function.
This simplifies driver development and
maintenance significantly by separating the
peripheral functions logically into different
device drivers.
The Xilinx PCIe hardblocks in the 7 Series
device family however do not support more
than one physical PCIe function and do not
support multifunction devices natively.
Smartlogic's new patented multifunction
extension IP-Core removes this restriction by
extending the Xilinx PCIe hardblock with up to 6
physical PCIe Functions. Compared to a PCIe
soft IP core solution with multifunction support,
the Smartlogic IP core uses only a fraction of
logic resources and will fit even in the smallest
Artix FPGA devices.
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