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| 供应商 | Eureka |
|---|---|
| 型号 | Industrial Standard Transparent PCI-to-PCI bridge |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Fully supports PCI bus specification 3.0 and PCI bridge specification Independent asynchronous PCI clocks on primary and secondary bus Transparent design does not require any software modifications. All devices operates as if all are on the same bus. Dual write buffer on each direction supports posted memory write Supports prefetchable and non-prefetchable memory read with user specified prefetch limits Delay transaction processes IO read/write, configuration read/write and memory read transactions Follows transaction ordering and bypass rules as required by bus specification Supports target retry, disconnect, master abort and target abort terminations Includes all PCI-PCI bridge specific configuration registers Optimized for ASIC and FPGA implementations |
| 详情页 | View more |
| 附件链接 | View more |
The PCI-to-PCI bridge is designed for bridging between the primary PCI bus and the secondary PCI buses. This is a fully transparent bridge that allows the system to expand the PCI bus into multiple segments and increase bus bandwidth.
The PCI-to-PCI bridge fully conforms with the PCI transparent bridge specification so no software modification is needed. All the devices function in the same way as if they were all in the same bus. The bridge follows the transfer ordering, error propagation per specification. Posted write access are delay read are implemented with internal data FIFO.
The primary and secondary PCI buses may operate at different clock domains as the PCI-PCI bridge handles all domain crossing requirements.
The EP440 transfer access from the primary PCI bus to the secondary PCI bus and vice versa based on address mapping. The EP440 consists of bus master, bus target, configuration initiation functions, and all the required data and command FIFO between the two buses.
The PCI-to-PCI bridge fully conforms with the PCI transparent bridge specification so no software modification is needed. All the devices function in the same way as if they were all in the same bus. The bridge follows the transfer ordering, error propagation per specification. Posted write access are delay read are implemented with internal data FIFO.
The primary and secondary PCI buses may operate at different clock domains as the PCI-PCI bridge handles all domain crossing requirements.
The EP440 transfer access from the primary PCI bus to the secondary PCI bus and vice versa based on address mapping. The EP440 consists of bus master, bus target, configuration initiation functions, and all the required data and command FIFO between the two buses.
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