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| 供应商 | Arasan Chip Systems |
|---|---|
| 型号 | Octal SPI Host Controller IP |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | No configuration start. The OctalSPI IP defaults into SPI mode (1S-1S-1S) upon reset, with a command 8’h03 and access to the first 16MB of external address space. AXI - Either AXI3 or AXI4 support, with a parameterized bus width ranging anywhere from 16 bits to 1024 bits wide. Support for protocols: SPI, Dual SPI, and Quad SPI Supports up to four external devices via the CS# signal. Commands that cross devices, such as extended DMA reads or writes, will naturally be split between device boundaries Arbitrary command support • Arbitrary SPI, Dual SPI, or Quad SPI commands may be issued and read. Such com- mands may be necessary to place the interface into any arbitrary desired mode Memory mapped write support, for those devices supporting writes • The write command may be arbitrary • The write capability can be selectively turned off for those designs that do not support it Optional I/O support. The OctalSPI IP supports the optional IO bits: RSTO#, WP#, INT#, and ECS#. |
| 详情页 | View more |
| 附件链接 | View more |
Arasan Chip System’s Octal SPI master controller is designed to be a simple and hands off, yet high speed Octal SPI controller. It makes reading from an external flash device, using this controller, as simple as reading from the main AXI3 or AXI4 slave port. An AXI4-lite control port provides access to both the raw Octal SPI interface, but it also provides the ability to control the SPI sub-protocol used for all subsequent transactions with great flexibility. Using the AXI4-lite port, the controller may be configured to support most SFDP protocols. This includes the ability to write to write to devices that support it. High speed DMA operation is possible via a separate AXI master port designed for that purpose.
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