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| 供应商 | Noesis Technologies |
|---|---|
| 型号 | XTS mode AES Processor |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Supports high throughput AES XTS mode for data storage applications Compliant with IEEE 1619-2007and NIST SP800-38E recommendations Supports 128-bit data-path width Supports 128 bit (XTS-256 mode) or 256-bit (XTS-512 mode) key sizes Supports cipher stealing mode an be configured either as an encryptor or decryptor mode of operation Provides a throughput rate of 16 Gbps at 125 MHz clock rate Fully synchronous design, using single clock with simple parallel user interface Scalable architecture for optimal area/performance trade off Portable to any ASIC or FPGA technology for a variety of applications |
| 详情页 | View more |
| 附件名称 | ntAES_XTS_pb.pdf |
| 附件链接 | View more |
The ntAES_XTS IP Core is fully compliant with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations targeting disk encryption applications at sector (data unit) addressable level. It is also known as a tweakable block cipher where the encryption process is controlled by the tweak a 128-bit value that is generated from the actual logical position of the data unit on the disk. This way identical data units stored at different places will result in different encrypted data thus addressing copy-and-paste attacks. Each data unit size is at least 128-bits. In addition each data unit size can be either an integral or non-integral number of 128-bit blocks. In case where the data unit size is not divisible with 128 then the ciphertext stealing procedure is used to enable correct encryption of the last block. Due to its highly parameterized and scalable architecture the users can trade off logic resources and performance in order to achieve optimum match with their application requirements. The implementation is low on latency, high speed with a simple interface for easy integration in SoC applications.
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