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| 供应商 | Arasan Chip Systems |
|---|---|
| 型号 | Arasan LLI Controller compliant to MIPI Low Latency Interface Spec Ver 1.0 |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Compliant with MIPI LLI Rev 1.0 and M-PHY Type 1 Rev 2.0 Interfaces to on-chip interconnect infrastructure, like AHB or AXI or OCP buses Configurable to provide master and/or slave interfaces to AXI/AHB/OCP buses Provides AHB/AXI/OCP Slave Interface for PHY Adapter Layer management Uses Arasan's LLI specific MPHY TYPE-1 as the physical layer running at HS Gear 1 and 2, and PWM Gears 0-7 Implements Transport/Data Link Layers of the LLI Specification Implements PHY Adapter Layer based on the number of configured M-PHY lanes Minimal latency across all the LLI layers Supports test features as specified in the LLI specification |
| 详情页 | View more |
| 附件链接 | View more |
The Low Latency interface (LLI) is a point-to point-interconnect that allows two devices on the separate chips to communicate as if a device attached to or present on the remote chip is resident on the local chip. The connectivity to the remote chip's devices is through standard interconnects (AHB/AXI/OCP), using memory mapped transactions.
LLI is expressed as a layered transaction level protocol, where the Initiator and Target devices on two linked chips exchange transactions without software intervention. LLI supports two types of traffic classes, Low Latency and Best Effort. LLI primarily targets low-latency cache refill transactions using the Low Latency (LL) traffic class, and uses the Best Effort (BE) traffic class for accessing all other memory mapped remote devices. LLI also provides a special set of high priority transactions for transmitting sideband signals, like interrupts, between two chips connected with LLI link.
Arasan's LLI Controller resides on each instance of a chip pair, and the two controllers communicate at a physical level through the M-PHY and their associated differential signals. The LLI Controller IP requires Arasan's LLI specific MIPI M-PHY Type I IP as the Physical Layer and supports 1, 2, 3, 4 or 6 Lanes. The LLI Controller/M-PHY pairs on each chip together form a Low Latency Interface (LLI) bridge between the system buses/interconnects of two companion chips. This core is designed to be configurable as either a system bus master or slave, or both, for the Low Latency (LL) and Best Effort (BE) traffic classes defined in the MIPI LLI specification.
LLI is expressed as a layered transaction level protocol, where the Initiator and Target devices on two linked chips exchange transactions without software intervention. LLI supports two types of traffic classes, Low Latency and Best Effort. LLI primarily targets low-latency cache refill transactions using the Low Latency (LL) traffic class, and uses the Best Effort (BE) traffic class for accessing all other memory mapped remote devices. LLI also provides a special set of high priority transactions for transmitting sideband signals, like interrupts, between two chips connected with LLI link.
Arasan's LLI Controller resides on each instance of a chip pair, and the two controllers communicate at a physical level through the M-PHY and their associated differential signals. The LLI Controller IP requires Arasan's LLI specific MIPI M-PHY Type I IP as the Physical Layer and supports 1, 2, 3, 4 or 6 Lanes. The LLI Controller/M-PHY pairs on each chip together form a Low Latency Interface (LLI) bridge between the system buses/interconnects of two companion chips. This core is designed to be configurable as either a system bus master or slave, or both, for the Low Latency (LL) and Best Effort (BE) traffic classes defined in the MIPI LLI specification.
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