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| 供应商 | Cadence |
|---|---|
| 型号 | DSI transmitter controller for application |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compliant with MIPI DSI v1.3.1 Supports both Command Mode and Video Mode Supports bi-directional low-power data transmission (LPDT) Cadence Serial Display Interface (SDI), MIPI Display Pixel Interface (DPISM), and Display Compression (DSC) input interface options Connects to MIPI D-PHY lane modules through PPI (up to 4 data lanes) Provides protocol error detection Programmable test video generator for integration debug and test 32-bit Arm? AMBA? 3 Advanced Peripheral Bus (APB) responder interface for register access |
| 详情页 | View more |
| 附件链接 | View more |
The Cadence? Transmitter (TX) Controller IP for MIPI DSI is compliant with the MIPI? Alliance Specification for Display Serial Interface (DSISM) version 1.3.1. The TX Controller IP for DSI provides the interface from a host device graphics controller to one or more display modules and includes an arbitration layer for arbitrating among the various data and command streams, a DSI protocol layer for protocol functions, a lane management layer (LML) to distribute the DSI data stream across the active D-PHYSM lane modules, and an external register interface for configuration of the controller IP and status/error reporting. The TX Controller IP for DSI is architected to rapidly and easily integrate into any system-on-chip (SoC), and to connect seamlessly to Cadence or third-party PPI-compliant D-PHY lane modules. The TX Controller IP for DSI provides a cost-effective, low-power solution for demanding applications. It offers SoC integrators the advanced capabilities and support that not only meet but exceed the requirements of high-performance designs and implementations. All Cadence IP for MIPI is silicon proven and has been extensively validated with multiple hardware platforms.
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