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MIPI DSI Peripheral Controller IP Core HIP3510-ip-21365
￥10,000.00
| 供应商 | HDL Design House |
|---|---|
| 型号 | MIPI DSI Peripheral Controller IP Core - HIP3510 |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Supports both command and video modes of operation Transmission packet sequences supported: burst mode, non-burst mode with sync events, non-burst mode with sync pulses Compliant to the MIPI specification DSI (Display Serial Interface) 1.02 Compliant to the MIPI specification DCS (Display Command Set) 1.02 Compliant to the MIPI specification DPI-2 (Display Pixel Interface) 2.0 Compliant to the MIPI specification D-PHY (Physical Layer Device) 1.0 Supports the following interfaces: Host processor - AMBA AHB (Advanced High- Performance Bus) 2.0. (I2C and custom interfaces are also available upon request) Supports D-PHY: PPI (PHY Protocol Interface) Supports Video interface: DPI |
| 详情页 | View more |
| 附件名称 | HIP3510.pdf |
| 附件链接 | View more |
The HIP 3510 is a highly configurable, synthesizable digital IP core, used to exchange pixels and command data between a video source (host processor) and a display peripheral. Designed for use in portable electronic devices such as media players, mobile phones, and personal assistant devices, HIP3510 is fully compliant to MIPI Alliance's DSI, DPI-2, and DCS standards, as well as to AMBA's AHB specification. The video data is provided from an external D-PHY using either the HS (High Speed) or LP (Low Power) reception modes via a PPI interface, then processed by the HIP 3510 logic according to the DSI and DCS specifications., The output video data stream is sent to the DPI-2 or DBI interface. Figure 1 represents DSI Peripheral block level diagram. This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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