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| 供应商 | T2M |
|---|---|
| 型号 | MIPI D-PHY Physical Layer |
| 类型 | Hard IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Compliant to MIPI D-PHY version 1.0 or v1.1 and backward compliant to version 0.90. Compliant to MCNN, MFAA and SCNN, SFAA MIPI configurations Forward High Speed from 80MHz up to 800Mbps (65nmLP, 55nmLP), 1.0Gbps (40nmLP, 28nmLP), 1.5Gbps (28FDSOI) Supports MIPI D-PHY PHY Protocol Interface (PPI) and 1v2 GPIO mode 20MHz Bidirectional Low-Power Data Transmission (LPDT) Support Ultra Low-Power State (ULPS) & and triggers. IO are available during test mode for Scan |
| 详情页 | View more |
| 附件链接 | View more |
Our MIPI D-PHY Physical Layer provides a source synchronous, high speed, low power DPHY solution for mobile and low power applications. MIPI D-PHY configuration consist of one clock lane and one or more data lanes. D-PHY supports MIPI D-PHY v1.0 in 65nmLP, 55nmLP, 40nmLP and 28nmLP or v1.1 in 28FDSOI. D-PHY Receiver supports SMIA-CCP2 mode, both Data-Strobe and Data-clock mode up to 650MBps. Forward High Speed from 80MHz up to 800Mbps (65nmLP, 55nmLP), 1.0Gbps (40nmLP, 28nmLP), 1.5Gbps (28FDSOI)
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