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| 供应商 | T2M |
|---|---|
| 型号 | MIPI D-PHY Rx IP, Silicon Proven in SMIC 55LL |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2 Supports standard PPI interface compliant to MIPI Specification Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s Supports ultra-low power mode, high-speed mode and escape mode Supports one clock lane and up to four data lanes Data lanes support transfer of data in high-speed mode Supports error detection mechanism for sequence errors and contentions Supports contention detection |
| 详情页 | View more |
| 附件链接 | View more |
The D-PHY specification, version 1.2, is perfectly complied with by the MIPI D-PHY Analog RX IP Core. Supported protocols include the Display Serial Interface (DSI) and MIPI Camera Serial Interface (CSI-2). This RX PHY consists of one clock lane and four data lanes. The D-PHY is made up of an analogue front end for creating and receiving electrical level signals and a digital back end for managing I/O operations. internally terminated resistor that is automatically calibrated.
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