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| 供应商 | T2M |
|---|---|
| 型号 | LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Support data rate: 0.5Gbps~4.0Gbps configurable reference clock frequency Per-lane 10-bit/9-bit/8-bit/7-bit parallel interface Support Spread Spectrum clock generation: up to ±5000ppm@31.5KHz AC coupling, 75nF~200nF at both ends and one end in TX near-end. One shared PLL for all lanes Individually power down for each lane Support 0~9dB programmable 2-tap FFE (Feed forward equalization) Support data rate: 0.25Gbps~2.0Gbps |
| 详情页 | View more |
| 附件链接 | View more |
The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can be easily fabricated and implemented in a GVI, LVDS or MIPI DSI system. For GVI/LVDS system, Macro consists of multi-transmitter channels and one SU unit. The speed of transmitter macro is up to 4.0Gbps and can be configured to GVI (CML) or LVDS mode. For MIPI DSI system, a DSI configuration includes a Clock Lane Module and four Data Lane Modules.
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