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| 供应商 | Arasan Chip Systems |
|---|---|
| 型号 | MIPI CSI-2 Transmitter Controller |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compliant with Camera Serial Interface (CSI-2) version 1.01 and D-PHY 1.1 Connectivity to D-PHY through PPI Interface 1 to 4 data lane support Hi-Speed (HS) transmit rates of 80 Mbps to 1.5Gbps per lane Low Power (LP) transmit at 10 Mbps. Switching to and from Low Power (LP) and Ultra-low Power (ULPS) modes Camera Sensor Interface supports any byte aligned data format output from the camera sensor Support for all YUV, RAW and RGB data types listed in MIPI specification Microcontroller Interface for register configuration and monitoring using programmed IO |
| 详情页 | View more |
| 附件链接 | View more |
The Arasan CSI-2 Transmitter IP is designed to provide MIPI CSI 1.01 compliant high speed serial connectivity for camera modules in mobile platforms. Serial connectivity to the mobile applications processor's CSI receiver is implemented using 1 to 4 D-PHY lanes, depending on camera sensor resolutions and the resulting bandwidth needs. This IP connects to the D-PHY's through the PPI interface.
Initial configuration of this IP and its associated Arasan D-PHY can be done through programmed IO over a microcontroller bus, however, other bus interfaces can be provided upon request.
Pixel data received from over the Camera Sensor Bus is required to be in a byte aligned CSI-2 packet format. This IP calculates and appends an ECC value to a short packet or to the header of a long packet. For the payload of a long packet carrying pixel data, this IP calculates its CRC value and appends to the packet as a footer. The packet is buffered in a FIFO and sent to one or more D-PHY's depending on the lane distribution scheme set by the camera sensor.
Benefits
Fully compliant to MIPI standard
Small footprint
Code validated with Spyglass
Functionality ensured with comprehensive verification
Product quality proven with silicon
Premier direct support from Arasan IP core designers
Initial configuration of this IP and its associated Arasan D-PHY can be done through programmed IO over a microcontroller bus, however, other bus interfaces can be provided upon request.
Pixel data received from over the Camera Sensor Bus is required to be in a byte aligned CSI-2 packet format. This IP calculates and appends an ECC value to a short packet or to the header of a long packet. For the payload of a long packet carrying pixel data, this IP calculates its CRC value and appends to the packet as a footer. The packet is buffered in a FIFO and sent to one or more D-PHY's depending on the lane distribution scheme set by the camera sensor.
Benefits
Fully compliant to MIPI standard
Small footprint
Code validated with Spyglass
Functionality ensured with comprehensive verification
Product quality proven with silicon
Premier direct support from Arasan IP core designers
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