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| 供应商 | Arasan Chip Systems |
|---|---|
| 型号 | MIPI CSI-2 Receiver Controller |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compliant with MIPI Camera Serial Interface (CSI-2) version 1.01 Connectivity to D-PHY through PHY Protocol Interface (PPI) Interface One to four data lane support Hi-Speed (HS) receive rates of 80 Mbps to 1.5Gbps per lane Low Power (LP) data transfer at 10 Mbps Switching to and from Low Power (LP) and Ultra-Low Power (ULPS) modes IP core and external ISP interface support all data formats specified in CSI-2 spec Up to 4 image streams using virtual channels AHB interface for register configuration and monitoring using programmed IO IP core and external ISP interface support |
| 详情页 | View more |
| 附件链接 | View more |
The Arasan CSI-2 Receiver IP is designed to provide MIPI CSI 1.01 compliant high speed serial connectivity for applications processors to corresponding camera modules in mobile platforms.
Serial connectivity between this IP and an external the camera module's CSI transmitter is implemented using 1 to 4 D-PHY lanes, depending on camera sensor resolutions and the resulting bandwidth needs. This IP connects to the D-PHY's through the PPI interface.
Initial configuration of this IP and its associated Arasan D-PHY can be done through programmed IO over an AHB bus, however, other bus interfaces like AXI and OCP can be provided upon request.
This IP performs the data lane merging of image data received on PPI interface from D-PHY. It performs CRC and ECC checks to ensure the integrity of packet payload and header.
Based on the user register settings, the IP either forwards or drops the erroneous packets. All forwarded packet payloads are then converted from byte to pixel format, decompressed and output to an external Image Signal Processor (ISP) of the applications processor's graphics sub-system. All D-PHY Level errors, Packet Level errors and Protocol Decoding Level errors are communicated to the host from a status register.
Benefits
Fully compliant to MIPI standard
Small footprint
Code validated with Spyglass
Functionality ensured with comprehensive verification
Product quality proven with silicon
Premier direct support from Arasan IP core designers
Serial connectivity between this IP and an external the camera module's CSI transmitter is implemented using 1 to 4 D-PHY lanes, depending on camera sensor resolutions and the resulting bandwidth needs. This IP connects to the D-PHY's through the PPI interface.
Initial configuration of this IP and its associated Arasan D-PHY can be done through programmed IO over an AHB bus, however, other bus interfaces like AXI and OCP can be provided upon request.
This IP performs the data lane merging of image data received on PPI interface from D-PHY. It performs CRC and ECC checks to ensure the integrity of packet payload and header.
Based on the user register settings, the IP either forwards or drops the erroneous packets. All forwarded packet payloads are then converted from byte to pixel format, decompressed and output to an external Image Signal Processor (ISP) of the applications processor's graphics sub-system. All D-PHY Level errors, Packet Level errors and Protocol Decoding Level errors are communicated to the host from a status register.
Benefits
Fully compliant to MIPI standard
Small footprint
Code validated with Spyglass
Functionality ensured with comprehensive verification
Product quality proven with silicon
Premier direct support from Arasan IP core designers
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