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LPDDR5/4/4x PHY IP for Samsung 14nm-ip-17816
￥10,000.00
| 供应商 | OPENEDGES Technology |
|---|---|
| 型号 | LPDDR5, LPDDR4/4x 14nm PHY, OPHY |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compliant for JEDEC standards for LPDDR5/4/4x with PHY standards DFI 5.0 Interface Compliant Supports 1,2, or 4 ranks Multiple frequency states PHY independent training and calibration Multiple DFICLK: CK ratios and DFICLK:CK:WCK ratio Tx and Rx channel equalization Voltage and temperature tracking of timing and impedance control circuit Flexible floor planning/bump mapping |
| 详情页 | View more |
| 附件链接 | View more |
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined to bring synergy for high performance and low latency. OPENEDGES' integrated IP solutions are market and silicon-proven, featuring advanced architectures and proprietary technologies that enable customers to shorten their design and verification processes.
The LPDDR5/4 Combo OPHY features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environments. This architecture enables LPDDR5/4 Combo OPHY to overcome issues with long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without interruption of data traffic. The programmable timing at the OPHY boundary combines flexibility with analog precision, resulting in low read/write latency between OMC and the LPDDR5/4 DRAM without sacrificing performance.
The LPDDR5/4 Combo OPHY was designed with subsystem and system-level considerations in mind. Built-in power management logic and advanced PLL design allow aggressive power state management and optimal system power usage.
At the system level, the LPDDR54 Combo OPHY was desinged to minimize package substrate layer and PCB layer requirements, enabling usage in cost-sensitive applications and application processors.
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