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| 供应商 | Cadence |
|---|---|
| 型号 | Lowest latency and highest data rates for data-intensive applications |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | LPDDR4X/4/DDR4 training with write-leveling and data-eye training Automotive temperature grade Internal and external datapath loop-back modes I/O pads with impedance calibration logic and data retention capability Multiple PLLs for maximum system margin Programmable clock delay (PVT compensated) on read and write datapaths for DQS alignment Per-bit deskew on read and write datapath |
| 详情页 | View more |
| 附件链接 | View more |
Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms, the DDR PHY IP is silicon proven and can provide customers with ease of integration and faster time to market. The DDR PHY IP is engineered to quickly and easily integrate into any system-on-chip (SoC), and is verified with the Denali DDR Controller IP as part of a complete memory subsystem solution. The DDR PHY IP is designed to connect seamlessly and work with a thirdparty DFI-compliant memory controller. The DDR PHY IP is developed and validated to reduce risk for the customer, so that their (SoC) can be first time right. Developed for and available early in the lifecycle of the most advanced semiconductor process nodes, the DDR PHY IP is designed to be robust under varying noise conditions and to have interoperability with various supplier memory chips. The DDR PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, Denali memory interface, analog, and systems and peripherals IP.
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