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| 供应商 | CAST |
|---|---|
| 型号 | Low-Latency 10/100/1000 Ethernet MAC |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Low-Latency Ethernet MAC (Egress latency: 10 Tx clock cycles. Ingress latency: 6 Rx clock cycles). Enables high-precision, sub-microsecond timing synchronization. Host Interfaces: Avalon-MM for register access & Avalon-ST for packet data PHY Interfaces: MII for 10/100Mbps. GMII for 1Gbps. RGMII or 10/100/1000 Mbps & MDIO interface for PHY configuration and management Optional ISO-26262 ￠???“ASIL-D Ready￠??? Safety-Enhanced Version |
| 详情页 | View more |
| 附件链接 | View more |
The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. Featuring extremely low egress and ingress latency, the core is ideal for the implementation of TSN Ethernet nodes, live streaming and other devices requiring minimum latency in the reception and transition of Ethernet frames.
The core supports full-duplex operation, supports jumbo frames, provides statistics counters, and it is easy to integrate and implement. The LLEMAC-1G exchanges data with the host system via a byte-wide streaming interfaces, and connects to the external PHY via an MII, GMII or RGMII interfaces. An independently clocked, 32-bit wide memory mapped interface provides access to the cores control and status registers. The default core interfaces comply to the Avalon standard, but AMBA￠"?￠ AHB or AXI can also be made available upon request.
The LLEMAC-1G is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements clock activity monitors and uses spatial redundancy for protecting the inner logic of the core. The deliverables for this version include a Safety Manual (SAM);, a Failure Modes, Effects and Diagnostics Analysis (FMEDA);, and the ISO-26262 ￠???“ASIL-D Ready￠??? certificate, issued by SGS-T?“V Saar GmbH.
The core supports full-duplex operation, supports jumbo frames, provides statistics counters, and it is easy to integrate and implement. The LLEMAC-1G exchanges data with the host system via a byte-wide streaming interfaces, and connects to the external PHY via an MII, GMII or RGMII interfaces. An independently clocked, 32-bit wide memory mapped interface provides access to the cores control and status registers. The default core interfaces comply to the Avalon standard, but AMBA￠"?￠ AHB or AXI can also be made available upon request.
The LLEMAC-1G is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements clock activity monitors and uses spatial redundancy for protecting the inner logic of the core. The deliverables for this version include a Safety Manual (SAM);, a Failure Modes, Effects and Diagnostics Analysis (FMEDA);, and the ISO-26262 ￠???“ASIL-D Ready￠??? certificate, issued by SGS-T?“V Saar GmbH.
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