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| Supplier | CAST |
|---|---|
| Model | LIN Bus Master/Slave Controller Core |
| Type | Soft IP |
| Attachment - Source URL | View more |
| Due Date | In Production |
| Feature | Support of LIN specification 2.0, 2.1, and 2.2A Backwards compatible with LIN specification 1.3 Configurable for support of master or slave functionality Programmable data rate between 1 Kbit/s and 20 Kbit/s (for master) Automatic bit rate detection (for slave) 8-byte data buffer 8-bit host controller interface Wrappers for 32bit busses (e.g. APB) can be made available upon request Slave can be implemented with or without clock synchronization Optional acceptance filter enable slave core to transmit response frames without host assistance Fully synchronous design, available in VHDL or Verilog, completely synthesizable The LIN Controller synthesizes to approximate 2500 to 3800 gates depending on the configuration Robustly verified and multiple times production proven IP core |
| Source Details URL | View more |
| Source URL | View more |
The LIN core is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. The LIN controller can be implemented as a master or as a slave and operate on LIN 1.3, 2.0, 2.1 or 2.2 LIN network. It uses a single master/multiple slave concept for mes-sage transfer between nodes of the LIN network. The message transfer can be controlled via a micro controller interface and a LIN transceiver is needed for the connection to the LIN bus. The core can optionally be modified to implement a standalone slave controller that requires no assistance from a host processor to transmit response frames. The LIN core is a microcode-free design developed for reuse in ASIC and FPGA implementations. The scan-ready design is strictly synchronous with positive-edge clocking and no internal tri-states. The robustly verified core has been production proven multiple times.
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