JPEG-EX-S: Baseline and Extended JPEG Encoder-ip-22781

¥10,000.00
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SKU
ip-22781
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供应商 CAST
型号 Baseline and Extended JPEG Encoder Core
类型 Soft IP
到期日 In Production
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特征 Performs Baseline and Extended Sequential DCT JPEG encoding of images or video for ASICs or FPGAs, with small silicon area, high performance, and low latency. Standards Support ISO/IEC 10918-1 Standard Baseline and Extended Encoder (Sequential DCT modes) Single-frame JPEG images and Motion JPEG payloads 8-bit and 12-bit per color samples Up to four color components; any image size up to 64k x 64k All scan configurations and all JPEG formats APP, COM, and restart markers Programmable Huffman Tables and Quantization tables Rate Control Options Image: Limits the size of each individual frame Video: Regulates bit rate over a number of input frames Interfaces AXI Streaming I/O data interfaces APB Control/Status interface Performance and Size ? One encoded sample per clock cycle ? Small silicon footprint (about 80k ASIC gates) Ease of Integration Automatic program-once/encode-many operation Simple, dedicated timestamps interface Included bit-accurate software model generates test vectors, expected results, and core programming values Optional Raster-to-Block Conversion with AXI or standard memory interface to the lines buffer
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This JPEG compression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, ASIC or FPGA hardware JPEG encoder with very low pro-cessing latency. The JPEG-EX-S Encoder produces compressed JPEG images and the video payload for Motion JPEG container formats. It accepts images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it requires just 80,000 equivalent gates when mapped on an ASIC technology. Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA? interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface. Customers with a short time to market priority can use CAST's IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST. The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

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