PLL

Phase Locked Loops (PLLs) are used to lock and input and reference clock to a prescribed [fixed] phase relationship. They are typically used to remove propagation delay (phase shift) between an input reference clock and internal (on-chip) clock, but have a variety of other uses as well.

A0516-ip-14454
￥10,000.00
A0515-ip-14096
￥10,000.00
A0514-ip-12614
￥10,000.00