PLL

Phase Locked Loops (PLLs) are used to lock and input and reference clock to a prescribed [fixed] phase relationship. They are typically used to remove propagation delay (phase shift) between an input reference clock and internal (on-chip) clock, but have a variety of other uses as well.

A0203-ip-12144
￥10,000.00
A0365-ip-11534
￥10,000.00