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| 供应商 | CAST |
|---|---|
| 型号 | I2C-MS: I2C Bus Controller Master/Slave |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compliant to Philips I2C standard All I2C bus speeds, Standard (Sm), Fast (Fm), Fast Plus (Fm+), High-speed (Hs), and Ultra Fast modes (UFm). Both 7-bit and 10-bit slave addressing Supports single or multi-master buses Clock-Stretching to allow fast-master slow-slave communication Configurable Operation: Master, Slave, or Master/Slave Host Interface Options: APB, AHB, or Wishbone Slave |
| 详情页 | View more |
| 附件链接 | View more |
The I2C-MS core is a controller for the Inter-Integrated Circuit (I2C) bus. The highly configurable core can implement an I2C bus master, slave, or a combined master and slave, and it communicates with the host via an APB, AHB, or Wishbone slave interface.
The core supports all variations and configurations of I2C networks. It can be used in single- or multiple-master networks, running in any of bus standard-defined speeds, employing either 7-bit or 10-bit I2C slave addressing. Supporting clock stretching, it allows communication between slow slave and fast master.
Designed for ease of use and operation, the core allows choosing between master and slave operation, and setting up I2C transfers at runtime with few register accesses. The core reports its internal status and the I2C bus status via its registers but also with via a rich set of interrupts.
The core supports all variations and configurations of I2C networks. It can be used in single- or multiple-master networks, running in any of bus standard-defined speeds, employing either 7-bit or 10-bit I2C slave addressing. Supporting clock stretching, it allows communication between slow slave and fast master.
Designed for ease of use and operation, the core allows choosing between master and slave operation, and setting up I2C transfers at runtime with few register accesses. The core reports its internal status and the I2C bus status via its registers but also with via a rich set of interrupts.
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