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供应商	CAST
型号	Hardware RTP Stack for H.264 Stream Encapsulation
类型	Soft IP
到期日	Available on request
源网址	View more
特征	RTP Encapsulation for H.264 NAL Streams Compliant to RFC 3984 and RFC 6184 Enables control of RTP packet size Supports Fragment Unit Packet Run-time programmable maximum stream bytes per RTP packet NAL units transmitted in NAL unit decoding order Easier Integration For Faster Development Processor-less, standalone operation AMBA? - AXI Interfaces AXI4-Lite Control/Status register interfaces AXI4-Streaming interfaces for packet data Available pre-integrated with: H.264 Video Encoder cores from CAST UDP/IP Hardware Stack from CAST CAST, Altera, Xilinx, or other third-party eMAC core
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详情

Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates H.264/NAL streams to RTP packets that are compliant with RFC 3894 and RFC 6184. The H2642RTP can be directly connected to the output of an H.264 encoder to output RTP packets, which can subsequently be forwarded for UDP/IP or TCP/IP encapsulation. The hardware stack produces complete RTP packets, without the need for any host-processor assistance. Along with CAST's UDP/IP hardware stack, the H2642RTP core is ideal for offloading the demanding task of RTP/UDP/IP encapsulation from a host processor, and enables H.264 video streaming even in processor-less SoC designs. The core is easy to integrate in systems with or without a host processor. H.264 stream and RTP packet data can are input/output via dedicated streaming-capable interfaces, enabling direct connection to hardware video encoders and hardware stacks for UDP or TCP. Status and control registers are accessible by an AXI4-Lite interface. The H2642RTP core is available in RTL source or as a targeted FPGA netlist. Platforms integrating the core along H.264 encoder, UDP/IP, and eMAC cores, are also available from CAST, and can enable rapid development of video over IP systems.

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