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| 供应商 | VeriSilicon |
|---|---|
| 型号 | GSMC0.18um 12-Bit 8-Input 1M/200k SAR ADC |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Process: GSMC 0.18um flash process 1Poly 5Metal Resolution: 12-bit resolution DNL: +/-1.5 LSB, INL: +/-3 LSB Dual Data Rates: 1MSPS/200KSPS Analog Input Range: VREFH to AGND, could be rail-to-rail Analog Supply: 2.7-3.6V; Digital Supply: 1.8V 8 Single-Ended Analog Inputs Auto Power Down Low Power Consumption: 4850?W(@1MSPS) / 2170?W(@200kSPS), < 1uA (Auto power down mode) |
| 详情页 | View more |
| 附件链接 | View more |
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The ADC includes a 8-1 MUX and a core internal SAR ADC which consists of sample/hold circuits, a capacitive DAC, a comparator and logic control circuits. This IP is typically used in touch screen application. Some types of input may need reference voltage whereas the others may not, for example, when this IP acts as battery detector, external reference must be present and stable. In addition, the reference voltage input will be adjusted to allow encoding smaller analog voltage spanning to the full 12 bit resolution. The ADC has dual speed modes â€" 1M/200K - working in 200K mode could save some power. Moreover, it supports two running modes: free running and single running. In single running mode, SAR will switch to power down mode automatically so as to save power. The converter is designed to allow operation with the NSC800 and INS8080A derivative control bus, with TRI-STATE output latches directly driving the data bus. The A/D appears like memory addresses or I/O ports to the microprocessor and no interfacing logic is needed. It is also suitable for integrated auxiliary codec applications and multi-converter architectures in wireless or battery-operated products.
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