dwc_usb3_digital_controller-ip-21723

¥10,000.00
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SKU
ip-21723
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供应商 Synopsys
型号 USB 3.0 Digital Controller IP
类型 Soft IP
到期日 Available on request
源网址 View more
特征 Supports SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails Lowers overall system power by design Configurable data buffering options to fine-tune performance/area trade-offs Host supports SuperSpeed, High-Speed, Full-Speed, and Low-Speed operation Host Controller compatible with common operating systems that support the xHCI standard, such as Windows 8 and Linux Device supports SuperSpeed, High-Speed, and Full-Speed operation DRD supports either Host or Device operation
详情页 View more
附件名称 dwc_usb3_csds.pdf
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Synopsys provides designers with silicon-proven, configurable DesignWare? USB 3.0 Controllers that are compliant with the USB-Implementers Forum (USB-IF) USB 3.0 specification. The DesignWare USB 3.0 controllers provide the lowest possible gate count, efficient power management optimized with dual power rails, and USB 3.0 PIPE and USB 2.0 UTMI/UTMI+ interfaces for PHYs. This comprehensive solution also includes support for Dual Role Device (DRD), xHCI Host, Device, and Hub Controllers and SuperSpeed InterChip (SSIC), High Speed InterChip (HSIC), and OTG 2.0 features.

DesignWare USB 3.0 Controller IP offers the flexibility required for high-volume, fast turnaround consumer applications. Configuration options maximize SoC design performance and minimize CPU interrupts, while flexible parameters enable easy integration into low- and high-latency systems.

DesignWare USB Controller IP has shipped in over one billion units for leading electronics companies worldwide. Using DesignWare USB IP significantly reduces development time and engineering risk, bringing USB-based SoCs to market faster.

DesignWare USB IP is the most certified IP solution in the industry. With over 3,000 design wins, Synopsys' complete USB IP solution--consisting of controllers, PHYs, verification IP, drivers, and IP prototypes--enables designers to lower integration risk and speed time-to-market.

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