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| 供应商 | Synopsys |
|---|---|
| 型号 | USB 2.0 femtoPHY in UMC (28nm) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes Supports the USB 2.0 480 Mbps protocol and data rate (high-speed) Backwards compatible with USB 1.1 operating at 1.5 Mbps (low-speed) and 12 Mbps (full-speed) Integrates high-speed, mixed-signal custom CMOS circuitry designed to the UTMI+ Level 3 specification Can be used in USB device, host, or on-the-go applications USB-IF Certified Supports USB Type-C? connector standard |
| 详情页 | View more |
| 附件名称 | dwc_usb2_femtophy.pdf |
| 附件链接 | View more |
The Synopsys DesignWare? USB 2.0 femtoPHY provides designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer applications such as smartphones, tablets, digital TVs, and media players. Offering reduced silicon cost and longer battery life, the DesignWare USB 2.0 femtoPHY IP delivers 50% smaller die area and minimizes active and suspend power consumption.
The DesignWare USB 2.0 femtoPHY implements the latest USB battery charger version 1.2 and USB On-The-Go (OTG) version 2.0 specifications from the USB Implementer’s Forum (USB-IF).
Architected for the industry’s most advanced 1.8V process technologies, the USB 2.0 femtoPHY is designed with features created to minimize effects due to variations in foundry process, device models, packages, and board parasitics.
The DesignWare USB 2.0 femtoPHY builds on years of customer success with Synopsys’ silicon-proven USB PHY IP product line, which has been ported to over 100 process nodes and configuration combinations ranging from 180-nm to 14-nm. When combined with the DesignWare Host, Device or On-The-Go (OTG) digital controllers and verification IP, the DesignWare USB 2.0 femtoPHY delivers a complete low power and small die area solution for advanced system-on-chip (SoC) designs.
The DesignWare USB 2.0 femtoPHY implements the latest USB battery charger version 1.2 and USB On-The-Go (OTG) version 2.0 specifications from the USB Implementer’s Forum (USB-IF).
Architected for the industry’s most advanced 1.8V process technologies, the USB 2.0 femtoPHY is designed with features created to minimize effects due to variations in foundry process, device models, packages, and board parasitics.
The DesignWare USB 2.0 femtoPHY builds on years of customer success with Synopsys’ silicon-proven USB PHY IP product line, which has been ported to over 100 process nodes and configuration combinations ranging from 180-nm to 14-nm. When combined with the DesignWare Host, Device or On-The-Go (OTG) digital controllers and verification IP, the DesignWare USB 2.0 femtoPHY delivers a complete low power and small die area solution for advanced system-on-chip (SoC) designs.
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