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| 供应商 | Synopsys |
|---|---|
| 型号 | UCIe PHY for Advanced Package in TSMC N5, North/South Poly Orientation |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Data rates up to 16Gbps per pin Self-contained hard macro Self-calibrating and training Side band channel for initialization and parameter exchange Built-in self-test (BIST), internal loopback, and external PHY-to-PHY link test Flexible configuration: 64 RX and TX pins per module (advanced package) or 16 RX and TX pins per module (standard package) Built-in test and repair functionality with redundant pins to maximize yield NS (north, south) orientation, EW (east, west) possible |
| 详情页 | View more |
| 附件名称 | dwc_ucie_phy.pdf |
| 附件链接 | View more |
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible architecture supports standard and advanced package technologies and delivers up to 4Tbps bandwidth in a multi-module configuration. Supporting widely used protocols such as PCI Express and CXL and enabling latency-optimized NoC-to-NoC links with streaming protocols, the IP offers maximum performance, minimum latency and implementation flexibility. Synopsys UCIe PHY IP delivers high energy efficiency with an optimized architecture that uses clock forwarding and low-voltage signaling. The IP implements a comprehensive set of testability features to ensure known good dies and offers test and repair capabilities to improve package assembly yield. Robust die-to-die link operation is ensured with embedded training and calibration algorithms. Synopsys UCIe PHY IP interoperates with Synopsys UCIe Controller IP to deliver a complete, low-latency solution for die-to-die links in any package.
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