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| 供应商 | Synopsys |
|---|---|
| 型号 | SATA 6G PHY in UMC (40nm, 28nm) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Compliant with SATA/eSATA specification revision 3.3 Excellent performance margin and receive sensitivity Very low power design; up to half the power compared to conventional PHYs Sample ATE test vectors provided for complete at-speed production testing Includes on-chip scope and built-in diagnostics for fast system verification Small, cost-effective die size Support for hot pluggable devices Optional spread-spectrum clock generation and absorption (SSC) with down-spread programmable from -5000ppm to -3000ppm Support for power down modes: partial, slumber and power down |
| 详情页 | View more |
| 附件名称 | dwc_sata_csds.pdf |
| 附件链接 | View more |
The DesignWare Mixed-Signal PHY IP for SATA and eSATA is designed for use in SoC solutions. The PHY integrates seamlessly with the DesignWare SATA AHCI Host digital controller to reduce design time and achieve first-pass silicon success. The SATA PHY provides a cost effective solution that is designed to meet the needs of today’s SATA designs. While extremely low in power consumption and area, the DesignWare SATA PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity. The unique, advanced built-in diagnostics and sample automatic test equipment (ATE) test vectors available in the DesignWare PHY enable designers to implement complete at-speed production testing without expensive test equipment. Furthermore, the test vectors provide on-chip visibility into the actual link performance to quickly identify signal integrity issues.
The PHY includes a wide range of test capabilities including built-in per-channel BERTs, flexible fixed and random pattern generation, error counting on patterns or disparity, digital phase or voltage margining (bathtub curves), and built-in per channel scopes. The high-margin, robust SATA PHY architecture tolerates for manufacturing variations such as process, voltage and temperature. The SATA PHY passed interoperability testing utilizing industry-leading 65-nm, 40-nm, and 28-nm process technologies.
The PHY includes a wide range of test capabilities including built-in per-channel BERTs, flexible fixed and random pattern generation, error counting on patterns or disparity, digital phase or voltage margining (bathtub curves), and built-in per channel scopes. The high-margin, robust SATA PHY architecture tolerates for manufacturing variations such as process, voltage and temperature. The SATA PHY passed interoperability testing utilizing industry-leading 65-nm, 40-nm, and 28-nm process technologies.
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