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| 供应商 | Synopsys |
|---|---|
| 型号 | PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, 7nm) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Compliant with PCIe? 3.1, 2.1, 1.1, and PIPE specifications x1, x2, x4, x8, x16 lane configurations with bifurcation Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) L1 substate and SRIS support Power gating and power island Embedded bit error rate tester (BERT) and internal eye monitor Build-in Self Test vectors, PRBS generation and checker IEEE 1149.6 AC JTAG Boundry Scan Supports -40°C to 125°C junctions Supports optional wirebond and flip-chip packaging |
| 详情页 | View more |
| 附件名称 | dwc_pcie4_phy.pdf |
| 附件链接 | View more |
The multi-channel DesignWare? PHY IP for PCI Express? 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support.
Synopsys offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support.
Synopsys offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.
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Q4: How long will it take for my order to arrive after I make payment?
A4: Members who ship their orders within Inida should expect to receive their orders within 2 working days upon payment verification depending on the count of orders received.
If you experience delays in receiving your order, contact us immediately and we will help to confirm the status of your order.
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