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| 供应商 | Synopsys |
|---|---|
| 型号 | Integrity and Data Encryption (IDE) Security IP Module for PCIe 5.0 |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Compliant with PCI Express IDE specification High-performance AES-GCM based packet encryption, decryption, authentication Seamless integration with Synopsys controllers via TLP packet-based interface Support for PCIe 5.0, 4.0 and 3.0 data rates Customer configurable “ Aligns with PCIe controller™s configuration options “ Scalable data bus width: 128, 256, 512 “ Lanes: x1, x2, x4, x8, x16 Optimized for area, performance & latency Multi-stream support PCRC calculation & validation Efficient key control & refresh |
| 详情页 | View more |
| 附件链接 | View more |
PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers to their use in consumer electronics. PCI Express links carry high value information between the host and the peripheral and from endpoint to endpoint. The Synopsys DesignWare? Integrity and Data Encryption (IDE) Security IP Module for PCIe 5.0 provides confidentiality, integrity, and replay protection for Transaction Layer Packets (TLP) over PCI Express interfaces as defined in the PCI-SIG IDE specification. The security module integrates seamlessly with the DesignWare PCIe 5.0 controllers to accelerate SoC integration.
DesignWare IDE Security IP Module for PCIe 5.0
The IDE Security Module for PCIe 5.0 (Figure 1) supports maximum throughput in full-duplex for Rx and Tx directions. It provides efficient encryption/decryption and authentication of TLP packets, with optimized high-performance and low-latency AES-GCM cryptographic cores.
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