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| 供应商 | Synopsys |
|---|---|
| 型号 | MIPI C-PHY v1.0 D-PHY v1.2 RX 3 trios/4 Lanes - TSMC 7FF 1.8V, North/South Poly Orientation |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Compliant with the latest MIPI C-PHY and D-PHY specifications Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 4.5Gb/s per lane in highspeed modes C-PHY mode includes two or three trios, each supporting a maximum of 3.5Gs/s per trio in high-speed modes Multiple low-power modes, including shut-down, provides multiple test modes for increased reliability Ease of integration with the protocol controller layer by implementing the MIPI recommended PPI Reliable, high-speed interface for camera and display applications, reducing line count and minimizing cable wires and EMI shielding requirements |
| 详情页 | View more |
| 附件名称 | dwc_mipi_c-phy_d-phy.pdf |
| 附件链接 | View more |
Synopsys? integrated DesignWare C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY, for FinFET processes and compliant with the MIPI C-PHY and D-PHY specifications, operates at 4.5Gb/s per lane and 3.5Gs/s per trio respectively for a maximum speed of 24Gb/s. DesignWare C-PHY/DPHY addresses energy requirements by supporting low-power state modes and delivering below 1.3pJ/bit at maximum speed. The PHY offers built-in test capabilities, including pattern generator, logic analyzer, and loopback modes covering all circuits. The DesignWare C-PHY/D-PHY IP interoperates with Synopsys? ASIL B Ready ISO 26262 certified CSI-2 and DSI/DSI-2 controllers which support key features of the latest MIPI display and camera specifications.
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