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| 供应商 | Synopsys |
|---|---|
| 型号 | Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Accelerate interface IP subsystem development for complex protocols, such as DDR, PCIe?, USB, and Ethernet, as well as multiprotocol subsystems Meet critical project schedules by using Synopsys IP protocol and SoC design experts to configure and customize the pre-designed subsystem to the unique SoC requirements Minimize the subsystem integration effort through the use of pre-validated subsystem and verification tests focused on SoC integration Reduce overall development costs while enabling designers to focus on their key competencies Provide functionality and value over simple integration of a PHY and controller by including a common register interface between the PHY and controller, debug logic, and more |
| 详情页 | View more |
| 附件名称 | interface_ip_subsystem_ds.pdf |
| 附件链接 | View more |
Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges. With more IP and more complex interface protocols, the integration effort to incorporate all of the IP into an SoC can take much longer. Companies are spending as much on integration effort as they are on their IP while project schedules are getting shorter.
DesignWare Interface IP Subsystems, one part of the IP Accelerated initiative, reduce design risk and accelerate time-to-market. The DesignWare Interface IP Subsystems consist of pre-validated, fully integrated solutions that utilize Synopsys’ IP and tools for the specific SoC application. DesignWare Interface IP Subsystems reduce the overall effort and cost of assembling and integrating IP into an SoC, allowing designers to focus their efforts on differentiating their product and speeding time-to-market.
DesignWare Interface IP Subsystems, one part of the IP Accelerated initiative, reduce design risk and accelerate time-to-market. The DesignWare Interface IP Subsystems consist of pre-validated, fully integrated solutions that utilize Synopsys’ IP and tools for the specific SoC application. DesignWare Interface IP Subsystems reduce the overall effort and cost of assembling and integrating IP into an SoC, allowing designers to focus their efforts on differentiating their product and speeding time-to-market.
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