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| 供应商 | Synopsys |
|---|---|
| 型号 | HBM3 for controller |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | JEDEC HBM 3.0 DRAM DFI 5.0 complaint interface to HBM3 PHY Multiport Arm® AMBA® interface (4 AXI AXI„¢) with managed QoS or single-port host interface, per pseudo-channel Data rates up to 6.4 Gbps (DFI 1:1:2) (1.6 GHz controller clock) Up to 32 pseudo channels 16 to 64 banks per pseudo channel Channel density of 2Gb to 32 Gb Multiple stack height support SEC-DED ECC Data scrubbing |
| 详情页 | View more |
| 附件名称 | dwc_hbm3_controller_ds.pdf |
| 附件链接 | View more |
DesignWare HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates with the DesignWare HBM3 PHY IP via an extended DFI 5.0 interface to create a complete memory interface solution. The HBM3 controller with pseudo channel support and flexible configuration options enhances memory bandwidth. The Controller includes software configuration registers, which are accessed through the Arm AMBA APB v2.0 specification interface.
The DesignWare HBM3 Controller includes the advanced dynamic memory access command scheduler (eg. CAM, QoS), memory protocol handler (eg. refresh, refresh management), Power saving capabilities (eg. self-refresh, power down, DFI low power, frequency change), reliability features (Read/Write DQ parity, command access (CA) parity, single error correction”double error detection error correcting code”SEC-DED ECC), PHY management and DRAM maintenance control (controller update, PHY update, controller message) and pseudo-channel support.
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