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| 供应商 | Synopsys |
|---|---|
| 型号 | eUSB 2.0 PHY - TSMC N5 x1, North/South (vertical) poly orientation |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Designed for advanced process nodes (7nm and below) Minimizes effects due to variations in process, voltage, temperature, package, and board parasitics Supports USB 2.0 480Mbps (High Speed), 12Mbps (Full Speed), and 1.5Mbps (Low Speed) data rates Connects to Synopsys’ DesignWare USB 2.0, 3.0, 3.1, and 3.2 host, device, and dual role controllers Lowest power: Extended battery life in advanced mobile devices for eUSB2 chip-to-chip communication |
| 详情页 | View more |
| 附件名称 | dwc_eusb2.pdf |
| 附件链接 | View more |
The DesignWare? Embedded USB 2.0 (eUSB2) PHYs, eUSB2 Repeaters, USB digital controllers, verification IP, and IP subsystems expertise provides designers with a USB 2.0 IP solution for low-power mobile and consumer products such as smartphones, tablets, laptops, gaming and AR/VR, and wireless devices that are designed using the industry’s most advanced process nodes.
The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was originally defined in the USB 1.0 specification from 1994 and is required for backwards compatibility. The eUSB2 specification defines new, lower voltage USB signaling that is used for low power chip-to-chip communication. eUSB2 repeater converts between standard USB 2.0 and eUSB2 signaling levels, allowing legacy USB 2.0 devices to connect to a system-on-chip (SoC) with eUSB2 PHY.
DesignWare USB IP is built on years of customer success with Synopsys’ silicon-proven USB PHY product line, which has been ported to over 100 process nodes ranging from 180nm to 5nm. When combined with the DesignWare Host, Device or Dual Role digital controllers and verified using Synopsys’ verification IP, the DesignWare eUSB2 IP delivers a complete USB 2.0 solution for advanced SoC designs.
The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was originally defined in the USB 1.0 specification from 1994 and is required for backwards compatibility. The eUSB2 specification defines new, lower voltage USB signaling that is used for low power chip-to-chip communication. eUSB2 repeater converts between standard USB 2.0 and eUSB2 signaling levels, allowing legacy USB 2.0 devices to connect to a system-on-chip (SoC) with eUSB2 PHY.
DesignWare USB IP is built on years of customer success with Synopsys’ silicon-proven USB PHY product line, which has been ported to over 100 process nodes ranging from 180nm to 5nm. When combined with the DesignWare Host, Device or Dual Role digital controllers and verified using Synopsys’ verification IP, the DesignWare eUSB2 IP delivers a complete USB 2.0 solution for advanced SoC designs.
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