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| 供应商 | Synopsys |
|---|---|
| 型号 | DDR5/4 PHY in TSMC (16nm, 7nm) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Supports JEDEC standard LPDDR5, LPDDR4 and LPDDR4X SDRAMs Support for data rates up to 6400Mbps Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution DFI 5.0 controller interface PHY independent, firmware-based training using an embedded calibration processor Optional dual channel architecture for LPDDR5/4/4X modes, which facilitates two independent channels in less area versus two independent PHYs Support for up to 15 trained states/frequencies Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture Built-in anti-aging features to prevent effects of NBTI & HC |
| 详情页 | View more |
| 附件名称 | dwc_ddr5_4_phy_ds.pdf |
| 附件链接 | View more |
The Synopsys DesignWare? DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR5/4 SDRAM interfaces operating at up to 4800 Mbps. The DesignWare DDR5/4 PHY is ideal for systems that require highspeed DDR5/4 performance and high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 4 physical ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR5/4 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR5/4 I/ Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR5/4 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR5/4 PHY includes a DFI 5.0 interface to the memory controller and can be combined with Synopsys’ DDR5/4 controller for a complete DDR interface solution.
Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR5/4 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR5/4 I/ Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR5/4 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR5/4 PHY includes a DFI 5.0 interface to the memory controller and can be combined with Synopsys’ DDR5/4 controller for a complete DDR interface solution.
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