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| 供应商 | Synopsys |
|---|---|
| 型号 | DDR4/3 PHY in TSMC (16nm, 12nm, 7nm) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs High-performance DDR PHY supporting data rates up to 3200 Mbps PHY independent, firmwarebased training using an embedded calibration processor Supports up to 4 trained states/frequencies with |
| 详情页 | View more |
| 附件名称 | dwc_ddr43_phy_ds.pdf |
| 附件链接 | View more |
The Synopsys DesignWare? DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR4/DDR3/DDR3L SDRAM interfaces operating at up to 3200 Mbps. The DesignWare DDR4/3 PHY is ideal for systems that require high-speed DDR3/4 performance requiring high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 16 ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4/3 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR4/3 PHY includes a DFI 4.0 interface to the memory controller and can be combined with Synopsys’ Enhanced Universal Memory (uMCTL2) or Protocol (uPCTL2) controllers for a complete DDR interface solution.
Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4/3 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR4/3 PHY includes a DFI 4.0 interface to the memory controller and can be combined with Synopsys’ Enhanced Universal Memory (uMCTL2) or Protocol (uPCTL2) controllers for a complete DDR interface solution.
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Q4: How long will it take for my order to arrive after I make payment?
A4: Members who ship their orders within Inida should expect to receive their orders within 2 working days upon payment verification depending on the count of orders received.
If you experience delays in receiving your order, contact us immediately and we will help to confirm the status of your order.
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