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| 供应商 | Synopsys |
|---|---|
| 型号 | DDR3/2 PHY in TSMC (40nm) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Supports JEDEC SDRAM standards including LPDDR2, LPDDR/ Mobile DDR, DDR2, DDR3, DDR3L (1.35V) and DDR3U (1.2xV) Supports data rates from 0 to 1066Mbps GDSII-based œhard PHY avoids timing closure problems common with œsoft RTL-based DDR PHYs Designed for rapid integration with Synopsys Universal DDR memory controller for a complete DDR interface solution Includes application specific, multi-protocol DDR I/Os including programmable drive strength and ODT DFI 2.1 compliant controller interface |
| 详情页 | View more |
| 附件名称 | dwc_ddr3_2_phy_ds.pdf |
| 附件链接 | View more |
Synopsys DesignWare? DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM memories. The DDR3/2 PHY IP supports the entire range of DDR3 SDRAM speeds, from DDR3-800 through DDR3-2133, with backward compatibility provided for DDR2-667 through DDR2-1066 devices. The PHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR3/2 PHY is constructed from the following libraries of components: the application specific SSTL I/O library, a single address/command macro block and multiple byte wide data macro blocks instantiated as many times as required to accommodate the memory channel width. Finally, the DesignWare DDR3/2 PHY includes a PHY Utility Block (PUB) that is supplied as soft IP. The PUB contains the circuitry to calibrate and maintain the calibration of the DDR3/2 PHY?s delay lines, provide voltage and temperature based correction to the I/O drive impedance and ODT settings, the PHY configuration registers, testability circuitry such as the at-speed loopback controller and the DFI 2.1 interface.
A key component of the DesignWare DDR3/2 PHY is the extensive in system data training/calibration capability in order to maximize the overall timing budget and improve system reliability. The DesignWare DDR3/2 PHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling.
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