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| 供应商 | Synopsys |
|---|---|
| 型号 | Die-to-Die, 112G PHY, TSMC 7nm x16 |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Offers leading performance, power, and area / beachfront per terabit Includes 16 lanes of NRZ and PAM-4 transmitters or receivers Compliant with the OIF USR and XSR standards: CEI-112G and CEI-56G Implements robust clock forwarded and embedded clock recovery algorithms for additional flexibility Physical Medium Dependent (PMD) soft-layer includes power sequencing and calibration engines Implements RX scope and PRBS and pattern generator, matcher and error counter for BERT testing Non-destructive 2D eye monitor capability can be performed during mission-mode operation Shared PLLs allow maximum energy efficiency Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal paths |
| 详情页 | View more |
| 附件链接 | View more |
The DesignWare Die-to-Die PHY IP enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules (MCMs) for hyperscale data center, AI, and networking applications. The low-latency, low-power, and compact PHY supports NRZ and PAM-4 signaling from 2.5G to 112G data rates and is compliant with the OIF CEI-112G and CEI-56G standards for ultra-short reach (USR) and extrashort reach (XSR) links. The Die-to-Die PHY offers flexible layout for maximum bandwidth per die-edge by allowing placement of the square macros along all edges of the die. It deploys 16-lane transmit and receive macros for optimized segmentation on the multiple dies.
The robust DLL-based clock forwarded architecture enables high energy efficiency while supporting reliable links of up to 50 millimeters for large MCMs. The PHY enables multi-die connectivity over organic substrates, which helps reduce packaging costs as well as advanced, interposer-based packaging over shorter distances. The embedded bit error rate (BER) tester and nondestructive 2D eye monitor capability provide on-chip testability and visibility into channel performance. Besides the PMA and PMD, the PHY includes a raw-PCS to facilitate the interface with the on-chip network, regardless of the existing networking protocol. The Die-to-Die PHY IP is combined with Synopsys? comprehensive routing feasibility analysis, packages substrate guidelines, signal and power integrity models, and crosstalk analysis for fast and reliable integration into SoCs.
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