dwc_c10pcie3phy_tsmc-ip-20143

¥10,000.00
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SKU
ip-20143
Brand :
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供应商 Synopsys
型号 10G PHY for PCIe 3.0 in TSMC (16nm, 12nm, 10nm, 7nm)
类型 Hard IP
到期日 Available on request
源网址 View more
特征 Supports 1.25 to 10 Gbps data rates Supports PCI Express 3.1, SATA 6G, SGMII Supports x1 to x16 configurations Superior signal integrity acrosslossy backplanes enabled by adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE) Low active and standby power Spread Spectrum Clock (SSC) Separate Reference Clock Independent SSC (SRIS) Reference clock sharing for aggregated macro configurations PCI Express Aggregation and bifurcation PRBS generator and checker; Supports flip chip and wirebond packaging; Supports IEEE 1149.6 AC Boundary Scan; Supports -40C to 125C T
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附件名称 dwc_multi_protocol_10g_phy.pdf
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The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.

The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.

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