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| 供应商 | Synopsys |
|---|---|
| 型号 | L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | High-speed, 64-bit, dual-issue, 10-stage pipeline 64-bit virtual and 52-bit physical address space Multicore support for up to 12 HS CPUs and up to 16 user hardware accelerators per processor cluster Enhanced MMU with support for Linux and SMP Linux 4 KB to 64 KB instruction and data L1 cache Up to 16 MB L2 cache (HS68 and MP versions) Up to 16 MB instruction and data close coupled memory (CCM) 128-bit loads and stores per clock Register file supports 2 write ports and 2 read ports Fast context switching with up to 8 register files 32x32 multiplier Radix-4 hardware divider Up to 240 interrupts, with up to 16 configurable preemption levels Native ARM® AMBA® AXI™, AHB-Lite™ and ACE interfaces JTAG and Compact JTAG (cJTAG) debug interface |
| 详情页 | View more |
| 附件名称 | arc_hs6x.pdf |
| 附件链接 | View more |
The DesignWare ARC HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where highperformance and high clock speed are required. The processors can be clocked at up to 1.8 GHz in 16FFC processes (worst case, single core, base configuration) and offer outstanding performance delivering 3.0 DMIPS/MHz and 5.1 CoreMark/ MHz with a small area footprint and low power consumption. The ARC HS66 and HS68 processors are based on the advanced ARCv3 instruction set architecture (ISA) and pipeline, which provides leadership power efficiency and code density. The processors feature a 52-bit physical address space and can directly address memories up to 4.5 Petabytes (4.5x1015) in size. For applications requiring higher performance, Multicore Processor (MP) versions of the HS66 and HS68 are available with support for up to 12 HS CPU cores and up to 16 hardware accelerators in the processor cluster. The ARC HS66 features level 1 (L1) instruction and data cache and close coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications. The HS68 is designed for use in applications running Linux or SMP Linux. The HS68 has all the features of the HS66 plus support for L2 cache up to 16 MB and a Memory Management Unit (MMU).
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