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| 供应商 | Synopsys |
|---|---|
| 型号 | High-performance ARC HS3x and HS4x processors are optimized for GHz+ operating speeds with minimum area and power consumption |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, & a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems. ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets. |
| 详情页 | View more |
| 附件名称 | dw-processor-solutions.pdf |
| 附件链接 | View more |
The DesignWare? ARC? HS family of 32-bit processors is based on the scalable ARCv2 Instruction Set Architecture (ISA) and is optimized to deliver maximum performance efficiency (DMIPS/mW and DMIPS/mm2) making it ideally suited for embedded applications with high-speed data and signal processing requirements. All HS processors are available in single-, dual- and quad-core configurations.
The ARC HS3x Family includes the multicore-capable HS34, HS36 and HS38 processors. The HS34 is a high-performance cacheless processor, while the HS36 includes up to 64KB of instruction and data caches. The HS38, optimized for applications running Linux, has a full-featured memory management unit (MMU) supporting a 40-bit physical address space and page sizes up to 16 megabytes, giving designers the ability to directly address a terabyte of memory with faster data access and higher system performance.
The ARC HS4x/HS4xD Family, which includes the HS44, HS46, HS48, HS45D and HS47D processors, implements a dual-issue superscalar architecture that delivers up to 6000 DMIPS per core (16ff typical conditions). The HS46 and HS48 offer instruction and data caches (up to 64 KBs of each) and support for full Level 1 (L1) cache coherency. The HS48 also incorporates up to eight megabytes of Level 2 (L2) cache and a full-featured memory management unit (MMU) supporting symmetric multiprocessing (SMP) Linux. The HS45D and HS47D support more than 150 DSP-optimized instructions, delivering a unique combination of high-performance control and high-efficiency digital signal processing. To speed the execution of math functions, the HS45D and HS47D give designers the option to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a optional IEEE 754-compliant floating point unit (single- or double-precision or both). The ARC HS4xD processors are compatible with the ultra-low power ARC EMxD processors and have the same instruction set, making it easy to migrate code between the two processor families.
All ARC HS processors are highly configurable and extensible, enabling designers to tailor each HS processor instance on their SoC for the optimum balance of performance, power and area.
The ARC HS Family is supported by a robust ecosystem of software and hardware development tools, including the MetaWare Development Kit, a complete solution for developing, debugging, and optimizing embedded software on ARC processors, the MQX real-time operating system (RTOS) and a portfolio of third-party tools, operating systems and middleware from leading industry vendors through the ARC Access Program.
The ARC HS3x Family includes the multicore-capable HS34, HS36 and HS38 processors. The HS34 is a high-performance cacheless processor, while the HS36 includes up to 64KB of instruction and data caches. The HS38, optimized for applications running Linux, has a full-featured memory management unit (MMU) supporting a 40-bit physical address space and page sizes up to 16 megabytes, giving designers the ability to directly address a terabyte of memory with faster data access and higher system performance.
The ARC HS4x/HS4xD Family, which includes the HS44, HS46, HS48, HS45D and HS47D processors, implements a dual-issue superscalar architecture that delivers up to 6000 DMIPS per core (16ff typical conditions). The HS46 and HS48 offer instruction and data caches (up to 64 KBs of each) and support for full Level 1 (L1) cache coherency. The HS48 also incorporates up to eight megabytes of Level 2 (L2) cache and a full-featured memory management unit (MMU) supporting symmetric multiprocessing (SMP) Linux. The HS45D and HS47D support more than 150 DSP-optimized instructions, delivering a unique combination of high-performance control and high-efficiency digital signal processing. To speed the execution of math functions, the HS45D and HS47D give designers the option to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a optional IEEE 754-compliant floating point unit (single- or double-precision or both). The ARC HS4xD processors are compatible with the ultra-low power ARC EMxD processors and have the same instruction set, making it easy to migrate code between the two processor families.
All ARC HS processors are highly configurable and extensible, enabling designers to tailor each HS processor instance on their SoC for the optimum balance of performance, power and area.
The ARC HS Family is supported by a robust ecosystem of software and hardware development tools, including the MetaWare Development Kit, a complete solution for developing, debugging, and optimizing embedded software on ARC processors, the MQX real-time operating system (RTOS) and a portfolio of third-party tools, operating systems and middleware from leading industry vendors through the ARC Access Program.
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